- At best, a T-cycle of 500 nS (2 MHz). More realistic is a T-cycle of 1uS, but I have hope for 500 nS.
- All 8080 instructions as one can expect.
- This is not a complete computer, it is just the CPU. It has to be hooked up to a BUS with RAM, IO etc etc.
- All outputs is TTL 3S and all inputs is TTL aware.
- Built from scratch with some thousands transistors (KSP10 and SS9018) and some more schottky diodes (BAT42). And a lot of 1N4148 and resistors.
- Will be parallel microcoded (the only part using IC, 32Kx8 SRAM). The original 8080 was not microcoded as far I can see, but used a lot of gates instead.
- 72 instruction variants, up to 14 T-cycles (XTHL instruction) gives 1008 lines of microcode, each line has 48 bits.
- 2 types of machine cycles, FETCH and EXECUTE. FETCH can be started before current EXECUTE has finished.
- FETCH takes 3 T-cycles and is not (!) inluded in the microcode, but hard coded instead.
- Interrupt is special, if implemented at all. Instead of one (1) interrupt line with external circuitry feeding an instruction into the 8080 I plan to have 7 interrupt lines running through a 74148 8-Line to 3-Line Priority Encoder, triggering a RST1 to RST7 instruction.
- No extra T-cycle for IO operations. There will be a WAIT-line that IO circuits can yank down, if needed. WAIT will effectively freeze the CPU.
All circuit boards is made at my kitchen countertop. I have not found a PCB manufacturer I can afford so my circuit boards are a little crude.
I use ExpressPCB and CopperConnection. Also LTspice to iron out some kinks.